1. Field of the Invention
The present invention relates to a fabrication process of a fine pattern in a semiconductor device. More particularly, it relates to a method for forming a fine pattern in a semiconductor device which performs three etching steps after the silylation process in a fabrication process of a fine pattern of a top surface imaging (hereinafter referred to as a TSI) process thereby preventing the pattern from becoming rough occurs by either leaving photosensitive film residue on a non-pattern area or an irregular breaking of a silylation layer's edge portion, and thereby increasing the margin in the lithography process.
2. Description of the Prior Art
In recent times, following the current trend of requiring high-integration semiconductor device, a technology for forming a fine pattern has been developed.
Specifically, a photosensitive film pattern formed by a photolithography process has been widely used as a mask of etching or ion implantation in a fabrication process of a semiconductor device.
Accordingly, a fineness of the photosensitive film pattern, a stability of a fabrication process, a clear elimination after finishing the fabrication process, and a facilitation of a reworking operation that removes wrong photosensitive film pattern and then reforms a photosensitive film pattern, largely, affect a production yield and a reliability of the semiconductor device.
In the light of the foregoing, a conventional art will now be described with reference to FIGS. 1-7.
FIGS. 1-4 depict a process for forming a fine pattern in a semiconductor device according to the conventional art, and specifically depict an example of TSI process wherein a light-exposure area is patterned.
Referring to FIG. 1, an etched layer 12 and a photosensitive film 14 for silylation are sequentially formed on a semiconductor substrate 10, and then, a selective light-exposure process using a light-exposure mask 16 is performed.
Thereafter, a presilylation bake process is performed about the photosensitive film 14, and a silylation process that implants a silicon into a light-exposure area by using silylation materials such as a tetramethyldisilazane (hereinafter referred to as TMDS) and a hexamethyldisilazane (hereinafter referred to as HMDS) is then performed.
At this time, as shown in FIG. 2, nitrogen(N)--silicon(Si) coupling inside of a silylation material reacts with oxygen(O)--hydrogen(H) coupled inside of a photosensitive film resin, thereby forming O--Si coupling and a silylation region 18. Also, some silylations occur in a non-exposure area.
After that, in order to eliminate a photosensitive film residue, a first etching step performs an etching process about both the light-exposure area and the non-exposure area by using a mixed gas of fluorine(F)-based gas and oxygen(O) gas, and removes a silylation region 18 formed on the non-exposure area.
Then, as shown in FIG. 3, a second etching step uses an oxide film layer (not shown) as an etching boundary, and forms a photosensitive film 14's pattern by a dry type etching method using the oxygen gas. Herein, the oxide film is formed by coupling a silylation region 18 formed on the light-exposure area and the oxygen. In this case, a roughness remains on a side wall 14a of the photosensitive film 14's pattern.
As shown in FIG. 4, if the etched layer 12 that is being exposed by the use of the photosensitive film 14's pattern as a mask is etched until the semiconductor substrate 10 are exposed, the etched layer 12's pattern is formed. At this time, a side wall 12a of the etched layer 12 becomes rough.
The above method for forming a fine pattern in a semiconductor device according to the conventional art has the following disadvantages.
If the first etching step performs an etching process without using the fluorine-based gas in etching the photosensitive film pattern, the photosensitive film residue is left after the second etching step as shown in FIGS. 6-7.
Also, if the first etching step uses the fluorine-based gas in order to remove the photosensitive film residue, an edge portion of a silylation region formed on the light-exposure area are irregularly broken at the same time that a silylation region thinly formed on the non-exposure area is removed. Therefore, as shown in FIG. 5, a side wall of the photosensitive film pattern becomes rough.
Such roughness is transcribed in etching the etched layer, an irregular pattern is thus formed. As a result, a fabrication margin is decreased, and a production yield of the semiconductor device is lowered.